Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), may comprise user-programmable integrated circuits that can be programmed to implement user-defined logic circuits. At least some typical FPGA architectures (for example, a Virtex FPGA available from Xilinx, Inc. of San Jose, Calif.), may include an array of configurable logic blocks (CLBs), a programmable interconnect structure (PIP), programmable input/output blocks (IOBs), blocks of random access memory (BRAM), multipliers, digital signal processing (DSP) blocks, processors, clock managers, delay lock loops, and so forth. In many FPGAs the individual CLBs, PIPs, IOBs and the like may be associated with respective one or more configuration memory cells, the contents of which may determine how the associated resources are configured. To realize a particular user-defined circuit, configuration data may be loaded into the configuration memory cells and the resources, such as CLBs, PIPs, and IOBs, may be configured to realize particular circuit components for the user's circuit as defined by the configuration data.
Due to advancing semiconductor technology, the complexity of these types of devices has greatly increased. For example, programmable devices (PLDs) such as field programmable gate arrays (FPGAs) are now incorporating ever increasing numbers of functional blocks and more flexible interconnect structures to provide greater functionality and flexibility. With the increased number of resources, an ever-increasing amount of configuration memory and data to be stored in the configuration memory may be required to control multiplexers that connect signals to various destinations. Accordingly, one design consideration for PLDs may be the length of time to be consumed by the PLD configuration process. For example, depending on a variety of design considerations, it may be advantageous for configuration to be performed in a minimal amount of time, requiring greater bandwidth to transmit the configuration data. Such PLD users may thus require a configuration mode with high bandwidth capability that may interface to a specific, perhaps proprietary, bus standard.
PLDs typically include dedicated configuration circuitry implementing a limited number of standard configuration modes (e.g., serial, parallel, master, master-serial, etc.). These standard configuration modes are limited to those that the PLD manufacturer deemed useful and cost-effective to put on every PLD. However, these standard configuration modes might not meet the system requirements for a specific user, as described above. Lending flexibility to the standard configuration modes, some PLDs called self-reconfigurable PLDs may include an ability to reconfigure themselves. Thus, these PLDs can be initially programmed to implement a custom configuration mode, such as configuration over a soft PCI bus, configuration from a multi-gigabit transceiver (MGT), decompression of configuration data while configuring, decrypting configuration data while configuring, and so forth. When reconfiguring, however, a portion of the logic used to perform the configuration has typically required dedication to configuration of the PLD. In other words, the resources of such portion are not able to be overwritten without affecting the ability to configure the PLD, thereby limiting the ability to reconfigure the PLD. Accordingly, these portions of the configuration logic typically have not been subsequently available for alternative user-defined applications.
Thus, a typical design consideration for custom configuration logic in self-reconfiguring PLDs has been the amount and/or type of device resources needed for a particular PLD configuration mode. While one configuration mode may enable efficient configuration, the resources required therefor might not then be available to implement a particular user-defined circuit. If these resources are high value resources, the dedication to configuration may seem costly. PLD users may wish to avoid implementing such custom configuration modes in preference of lower cost solutions.
Thus, typical self-reconfigurable PLD embodiments show a compromise in the number of different available configuration modes that may be available relative to the extent and costs that may be associated with dedicating a number of resources of the PLD to configuration.
In designing a particular PLD, therefore, one or more of these considerations, such as time for configuration, flexibility in selection of configuration modes, security of configuration, number of resources available for application designs and the like, may be important. Flexibility for accommodating such considerations may benefit efficiencies and functionality of PLDs.